Makefile (1170B)
1 # Makefile for C projects 2 3 # options 4 CC = gcc 5 LINKER = $(CC) 6 CFLAGS = -O0 -pthread -g -std=gnu99 7 LFLAGS = -ldl -lX11 -lXi -lm -lpthread -lavcodec -lavformat -lavcodec -lswresample -lswscale -lavutil -lm 8 9 TARGET = App 10 11 # directories 12 SRC_DIR = ../../source 13 BIN_DIR = ../../bin 14 INCLUDE = -I../../third_party/include 15 OBJ_DIR = $(BIN_DIR)/.obj 16 17 # finds source files two directories deep 18 SOURCES = $(wildcard $(SRC_DIR)/*.c $(SRC_DIR)/*/*.c) 19 OBJECTS = $(SOURCES:$(SRC_DIR)/%.c=$(OBJ_DIR)/%.o) 20 DEPENDS = $(SOURCES:$(SRC_DIR)/%.c=$(OBJ_DIR)/%.d) 21 22 .PHONY: all build run clean 23 24 all: build 25 26 build: $(BIN_DIR) $(DEPENDS) $(BIN_DIR)/$(TARGET) 27 28 $(BIN_DIR): 29 mkdir -p $@ 30 31 # update dependencies 32 $(OBJ_DIR)/%.d : $(SRC_DIR)/%.c 33 @mkdir -p $(@D) 34 @echo -n "$(@D)/" > $@ 35 @$(CC) $(CFLAGS) -MM $< | sed "s/ /\t/" >> $@; 36 @echo "Updating dependencies for $<" 37 38 # add dependencies 39 include $(DEPENDS) 40 41 # compile 42 $(OBJ_DIR)/%.o : $(SRC_DIR)/%.c 43 @mkdir -p $(@D) 44 $(CC) -c $(INCLUDE) $(CFLAGS) $< -o $@ 45 46 # link 47 $(BIN_DIR)/$(TARGET): $(OBJECTS) 48 $(LINKER) $(OBJECTS) $(LFLAGS) -o $@ 49 50 run: build 51 ./$(BIN_DIR)/$(TARGET) 52 53 clean: 54 rm -f $(OBJECTS) $(GS_OBJ) 55 rm -f $(BIN_DIR)/$(TARGET)